Migration from 16 Megabit to 64 Megabit Flash Memory Devices Application Note This document will assist board-designers in creating a seamless migration path from AMD 16 Mb or 32 Mb low voltage (LV) flash and Simultaneous Read/Write (DL) devices to higher densities. Migration to a higher density may be necessary when the OS or system code becomes too large to fit in the current device. Another type of migration between families (LV to DL) may be useful to your system by allowing the storage of code and data in one device; thus reducing chip count. This transition between LV and DL families and/or the transition to higher densities can be simple if a few precautions are taken during the design phase of the PCB. devices will only accept 8.5-9.5 V on the ACC input. The LV devices, however, will accept 8.5-12.5 V on the ACC input. More details on the necessary modifications follow: DL16x LV160 * DL32x DL64x LV320 LV640U TSOP Migration Summary The Low Voltage (LV) and the Simultaneous Read/ Write (DL) families are pin-for-pin compatible in 8 Mb densities and below. In 16 Mb, the parts have the same pin-out except for the addition of the WP#/ACC pin to the Simultaneous Read/Write part. In order to use the Am29LV160 and the Am29DL16x interchangeably, either 0 V or 3 V must be placed on WP#, Pin 14; 0 V to protect boot sectors in the Am29DL16x or 3 V to leave the boot sectors unprotected. There are no internal pull-up resistors on this pin; therefore, it cannot be left floating. The DL migration from 16 Mb to 64 Mb is a seamless migration (see Figure 1); No hardware changes are necessary. Migration in the LV family is seamless up to 16 Mb and again from 32 Mb and above. When migrating from an LV part 16 Mb and below to an LV part 32 Mb and higher there are slight pin-out modifications that need to occur. The 32 Mb and higher LV parts include WP# and ACC pins not included on 16 Mb and below LV devices. Unlike the DL device with the WP#/ACC pin, the WP# pin and the ACC pin on LV devices have internal pull up resistors and can be left floating when not in use. When using the ACC function, the voltage levels differ between Am29LV (conventional 3 volt-only) and Am29DL (3 voltonly, Simultaneous Read/Write) devices. The Am29DL . * Three pin change Note: Devices in bold italics have not been introduced. Figure 1. 48 Pin TSOP Migration Migration Details From Am29LV160 To Am29LV320 The migration from the Am29LV160 to the Am29LV320 in TSOP is done with a modification of one jumper. Figure 2 shows that Pin 9, A19, needs to be re-routed to Pin 15. In order to design-in a path to eventually migrate to the Am29LV640 without re-spining the PCB, a jumper is required on Pin 9 to select between signals A19 and A21. Pin 13 and Pin 14 become the ACC and WP# pin, respectively. These two pins can be left floating. If you want to have write protect (WP#) functionality for the boot sectors, you must have the ability to control Pin 14. No changes are required for Pin 47, assuming that the Am29LV160 was operating in a x16 configuration and the Am29LV320 will be used in a 3 V system. If the Am29LV160 device was used in a x8 configuration, please see migration to the Am29DL32x device. Also, if the Am29LV320 is going to be used on a 5 Volt bus, 5 Volts needs to be placed on pin 47. Publication# 22935 Rev: B Amendment/0 Issue Date: September 13, 1999 Am29LV640 Am29LV320 Am29LV160 A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE# RESET# ACC WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 A15 A14 A13 A12 A11 A10 A9 A8 NC A20 WE# RESET# ACC WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 Figure 2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Am29LV160 Am29LV320 Am29LV640 A16 BYTE# A16 VIO A16 VIO VSS VSS VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 CE# A0 CE# A0 TSOP Am 29LVxxx Device Migration From Am29DL16x To Am29LV320 From Am29DL32x To Am29LV640 This migration is similar to the Am29DL32x Am29LV640 migration except for the need to route signal A21. Migrating from the Am29DL32x to the Am29LV640 in TSOP is more involved and requires jumpers on the PCB to allow for the four pin change. No changes are necessary to pin 47 (BYTE# VI/O) in TSOP if the Am29DL32x was used in a x16 configuration and the Am29LV640U is going to be used on a 3V bus. In this case, the BYTE# pin, pin 47, on the Am29DL32x will be tied high because it is in x16 mode. This will translate directly over to a 3 Volt I/O on the VI/O pin. If the Am29LV640U is going to be used on a 5 Volt bus, 5 Volts needs to be placed on pin 47. If the Am29DL32x was used on a x8 bus you must upgrade the interface to a x16 bus width to migrate to the Am29LV640U. From Am29LV160 To Am29DL32x This migration is necessary to take advantage of simultaneous functionality or if the system bus width is x8. The Am29LV320 is a x16 device only and does not support a x8 bus width. The Am29DL32x requires the addition of A20 to pin 10. In addition, pin 14 allows for WP#ACC functionality. Pin 14 cannot be left floating. For more information on WP#/ACC functionality please refer to the Am29DL32x data sheet at: http:// www.amd.com/products/nvd/techdocs/techdocs.html. From Am29LV320 To Am29LV640 Migrating from the Am29LV320 to the Am29LV640 in TSOP is simple because it is a direct migration. In the board design phase, allow for an additional address pin on pin 9. Pin 9 on the Am29LV320 is a No Connect (NC) and becomes A21 in the Am29LV640. This additional address pin will need to be routed at the time the Am29LV320 is designed into the system. 2 List of Pin Changes (See Figure 3) Pin 9 (A19 A21) Pin 13 (NC ACC) Pin 14 (WP#/ACC WP#) Pin 15 (RY#/BY A19) A19 re-routes from pin 9 to pin 15 using a jumper to allow for proper functionality in each density. Pin 13 and Pin 14 become the ACC pin and the WP# pin, respectively, on the Am29LV640. On the Am29DL32x device, Migration from 16 Megabit to 64 Megabit Flash Memory Devices both functions are implemented into Pin 14. It is best to devote two traces to these signals, even when using the Am29DL32x. The signals can be combined with a jumper when using the Am29DL32x and routed separately to the appropr iate pins when using the R2 Am29LV640. RY#/BY functionality is not available in both the Am29LV320 and the Am29LV640U. Figure 3 is an illustration of the recommended jumper configuration. Pin # DL16x DL32x LV320 LV640U 9 A19 A21 10 A20 A20 A21 A19 R1 ACC WP# R1 R2 11 WE# WE# 12 RESET# RESET# 13 NC ACC 14 WP#/ACC WP# 15 RY/BY# A19 RY/BY# R1 Note: This layout allows both DL16x/32x and LV320/640 families to function fully in a system design. Either R1 or R2 "Zero Ohm" resistors should be installed. Figure 3. TSOP Migration from 16 Mb and 32 Mb DL Devices to 32 Mb and 64 Mb LV devices FBGA Migration Summary The FBGA migration path is very simple as indicated in Figure 3. The footprint remains the same from 4 Mb to 16 Mb in a 48-ball FBGA package. An additional address pin needs to be accounted for when migrating from 4 Mb to 8 Mb and also when migrating from 8 Mb to 16 Mb. The number of balls changes from 48 to 63 when migrating from 16 Mb to 32 Mb; However, the signal placement of the 48 central balls remain the same. The outer balls or outrigger balls are used for package stability and not for routing signals. These ball configurations are shown in Figure 5. The NC (no connect) balls outside of the central 48-ball array are the outrigger balls. DL16x * DL32x DL64x LV160 * LV320 LV640U * 48 to 63 ball migration Figure 4. 16 Mb to 64 Mb FBGA Migration Migration from 16 Megabit to 64 Megabit Flash Memory Devices 3 63-ball FBGA 8 A B NC NC C NC E F G H J K 48-ball FBGA A 7 D NC 6 A13 B C D E A12 A14 A15 A16 A8 A10 F VIO G H BYTE# D15 VSS A11 DQ7 DQ14 DQ13 DQ6 6 5 A9 5 4 WE# RESET# A21 A19 DQ5 DQ12 VCC DQ4 4 RY/ 3 BY# WP# ACC A18 A20 DQ2 DQ10 DQ11 DQ3 3 2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 1 A3 A4 A2 A1 A0 CE# OE# VSS 2 NC 1 NC NC L M NC NC NC NC NC NC NC NC Am29LV160 Am29DL16x Am29LV32x Am29DL32x Am29LV64x Am29DL64x Figure 5. FBGA Migration (Top View, Balls Facing Down) A few notes to make about Figure 5: The V I/O pin on the Am29LV32x and Am29LV64x is a byte pin on all other listed parts. The Am29LV160 does not have the WP#/ACC pin. The Am29LV32x/64x have only ACC pins, and all other parts listed have both WP# and ACC on the same pin. When using the ACC function, the voltage levels differ between Am29LV (conventional 3 volt-only) and Am29DL (3 volt-only, Simultaneous Read/Write) devices. The Am29DL devices will only accept 8.5-9.5 V on the ACC input. The LV devices, however, will accept 8.5-12.5 V on the ACC input. Migration Details From Am29LV160 To Am29LV320 In contrast with the TSOP migration, the Am29LV320 device in FBGA still has Ready/Busy (RY#/BY) functionality. The addition of the ACC pin, previously a no connect (NC), has no impact because it can be left floating. The BYTE# pin becomes the V I/O pin. This also does not have an effect on the device if the Am29LV160 was operating in a x16 configuration and the Am29LV320 is going to operate on a 3V bus. From Am29DL16x To Am29LV320 This migration is similar to the Am29DL32x to the Am29LV640 migration except for the need to route signal A21. 4 From Am29LV160 To Am29DL32x Pin D4 (according to data sheet), previously a no connect (NC), becomes the WP#/ACC pin. This pin cannot be left floating. For more information on WP#/ACC functionality please refer to the Am29DL32x data sheet at: http://www.amd.com/products/nvd/techdocs/ techdocs.html. From Am29LV320 To Am29LV640 The FBGA Migration, like the TSOP, is also a direct migration. In the board design phase, allow for the additional address signal, A21 (see Figure 5). From Am29DL32x To Am29LV640 The addition of A21 needs to be taken into account during the design phase to allow ease of migration. In the FBGA package, the RY#/BY pin is still available. The BYTE# pin becomes the V I/O pin. This does not have an effect on the device if the Am29DL32x was operating in a x16 configuration and the Am29LV640 is going to operate on a 3 V bus. If the Am29LV640U is going to be used on a 5 Volt bus, 5 Volts needs to be placed on the V I/O pin. If the Am29DL32x was used on a x8 bus you must upgrade the interface to a x16 bus width to migrate to the Am29LV640U. Write Protect (WP#) functionality is no longer available because the WP#/ACC pin on the Am29DL32x becomes just an ACC pin on the Am29LV640. The ACC pin on the Am29LV640 can be left floating. In order to be able to protect sectors, you will need to perform a standard in-system or 12V Migration from 16 Megabit to 64 Megabit Flash Memory Devices sector protect. Remember, the 12 V sector protect is the only way to guarantee the same kind of protection achieved by the WP# pin. For more information on sector protection please see the application note entitled, "Reset Pin Circuitry for Flash Memory Sector Protection Management" at: http://www.amd.com/products/ nvd/techdocs/techdocs.html. SOFTWARE MODIFICATIONS Software changes that are necessary include modifications of the Device ID and sector architecture, and additional changes to the flash drivers to handle the density change. Please refer to ftp://ftp.amd.com/pub/ nvd/device_drivers/ for more information. AMD device drivers with detailed comments are located under the "v11" directory. The software located in this directory will need to be modified with every density change. CFI (Common Flash Interface) compliant devices eliminate the need for software modifications when using CFI drivers. Most AMD 16 Mb devices and above are CFI compliant (refer to individual part data sheet for confirmation). These CFI drivers will automatically handle things such as density changes. In order to take advantage of CFI compliance you must use the AMD CFI drivers located in the "cfi-v10" directory. The RY#/BY pin is no longer be available on the Am29LV320 and Am29LV640 in TSOP and the software will need to poll the DQ status bits. For more information on the DQ status bits, please see the product data sheet or refer to the application note, "Using the Operation Status Bits in AMD Devices" (PID# 22152). Even though the RY#/BY pin is still available when migrating in the FBGA package, it is a good idea to get into the habit of using the DQ status bits for determining the state of the flash device. The DQ Status bits give more information than the Read/Busy pin such as if the has device failed an operation and in which state it failed. In addition to the minor software modifications listed earlier, there may be additional changes necessary specific to Simultaneous Read/Write flash users. When migrating from a Simultaneous Read/Write Flash device (Am29DLxxx Flash) to a non-Simultaneous Read/ Write Flash device the user may have to remove a portion of code. If the software was written to take advant age of s imul tane ous operat ion s of th e Am29DLxxx Flash, the simultaneous functionality needs to be removed. If the software was not written to take advantage of the simultaneous functionality, no additional software changes need to occur. Migration from 16 Megabit to 64 Megabit Flash Memory Devices 5 REVISION SUMMARY Revision B (September 13, 1999) TSOP Migration Summary Clarified differences between the 29LV and 29DL device families regarding ACC. In Figure 3, corrected pin 14 for LV320 and LV640U to WP#. FBGA Migration Summary Clarified differences between the 29LV and 29DL device families regarding ACC. In Figure 5, changed the orientation to top view, balls facing down. Trademarks Copyright (c) 1999 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. 6 Migration from 16 Megabit to 64 Megabit Flash Memory Devices